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SN65LVDT41

Features: · Integrated 110-Ω Nominal Receiver Line Termination Resistor·Operates From a Single 3.3-V Supply·Greater Than 125 Mbps Data Rate·Flow-Through Pin-Out·LVTTL Compatible Logic I/Os·ESD Protection On Bus Pins Exceeds 16 kV·Meets or Exceeds the Requirements of ANSI/TIA/EIA-644A Standar...

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SN65LVDT41: Features: · Integrated 110-Ω Nominal Receiver Line Termination Resistor·Operates From a Single 3.3-V Supply·Greater Than 125 Mbps Data Rate·Flow-Through Pin-Out·LVTTL Compatible Logic I/Os·ESD...

SN65LVDT41 Data Sheet

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Part Number:
SN65LVDT41
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Integrated 110-Ω Nominal Receiver Line Termination Resistor
· Operates From a Single 3.3-V Supply
· Greater Than 125 Mbps Data Rate
· Flow-Through Pin-Out
· LVTTL Compatible Logic I/Os
· ESD Protection On Bus Pins Exceeds 16 kV
· Meets or Exceeds the Requirements of ANSI/TIA/EIA-644A Standard for LVDS
· 20-Pin PW Thin Shrink Small-Outline Package With 26-Mil Terminal Pitch


Application

· Memory Stick Interface Extensions With Long Interconnects Between Host and Memory Stick™
· Serial Peripheral Interface™ (SPI) Interface Extension to Allow Long Interconnects Between Master and Slave
· MultiMediaCard™ Interface in SPI Mode
· General-Purpose Asymmetric Bidirectional Communication


Pinout

Connection Diagram


Specifications

SN65LVDT14,
SN65LVDT41

 UNIT
Supply voltage(2) VCC

0.5 to 4

 V
Input voltage range D or R

0.5 to 6

 V
A, B, Y, or Z

0.5 to 4

 V

Electrostatic discharge

 Human body model(3), A, B, Y, Z, and GND-

±16

 KV
Human body model(3), all pins ±8 KV
Charged device model(4), all pins ±500 V

Continuous total power dissipation

See Dissipation Rating Table

Storage temperature range

65 to 150

  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

  

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.

(4) Tested in accordance with JEDEC Standard 22, Test Method C101.

 




Description

The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. It is designed to be used at the Memory Stick end of an LVDS based Memory Stick™ interface extension.

The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package.It is designed to be used at the host end of an LVDS based Memory Stick™ interface extension.




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