SN65LVP18

Features: ` Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs` Clock Rates to 1 GHz 250-ps Output Transition Times 0.12 ps Typical Intrinsic Phase Jitter Less than 630 ps Propagation Delay Times` 2.5-V or 3.3-V Supply Operation` 2-mm x 2-mm Small-Outline No-Lead PackageApplication· PECL-...

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SeekIC No. : 004497541 Detail

SN65LVP18: Features: ` Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs` Clock Rates to 1 GHz 250-ps Output Transition Times 0.12 ps Typical Intrinsic Phase Jitter Less than 630 ps Propagation Delay...

floor Price/Ceiling Price

Part Number:
SN65LVP18
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Features:

` Low-Voltage PECL Input and Low-Voltage  PECL or LVDS Outputs
` Clock Rates to 1 GHz
250-ps Output Transition Times
0.12 ps Typical Intrinsic Phase Jitter
Less than 630 ps Propagation Delay Times
` 2.5-V or 3.3-V Supply Operation
` 2-mm x 2-mm Small-Outline No-Lead Package



Application

· PECL-to-LVDS Translation
· Clock Signal Amplification



Specifications

    UNIT
VCC Supply voltage (2) -0.5 V to 4 V
VI Input voltage -0.5 V to VCC + 0.5 V
VO Output voltage -0.5 V to VCC + 0.5 V
IO VBB output current ±0.5 mA
  HBM electrostatic discharge(3) ±3 kV
  CDM electrostatic discharge(4) ±1500 V
  Continuous power dissipation See Power Dissipation Ratings Table


(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground (see Figure 1).
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A-7
(4) Tested in accordance with JEDEC Standard 22, Test Method C101




Description

SN65LVx18  is high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.

The SN65LVx18 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx19 defaults to 575 mV as well.

SN65LVx18  provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.
SN65LVx18  are characterized for operation from 40°C to 85°C.




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