SN65MLVD047

Features:

` Differential Line Drivers for 30-Ω to 55-Ω Loads and Data Rates(1) Up to 200 Mbps, Clock Frequencies
     up to 100 MHz
` Supports Multipoint Bus Architectures
` Meets the Requirements of TIA/EIA-899
` Operates from a Single 3.3-V Supply
` Characterized for Operation from −40 to 85
` 16-Pin SOIC (JEDEC MS-012) and 16-Pin TSSOP (JEDEC MS-153) Packaging


Application

· AdvancedTCA^TM(ATCA^TM) Clock Bus Driver
· Clock Distribution
· Backplane or Cabled Multipoint Data Transmission in Telecommunications, Automotive, Industrial, and Other Computer Systems
· Cellular Base Stations
· Central-Office and PBX Switching
· Bridges and Routers
· Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485

Pinout




Specifications

			UNITS
Supply voltage range(2), VCC			−0.5 V to 4 V
Supply voltage range(2), VCC		A, EN, EN	−0.5 V to 4 V
Output voltage range, VO		Y, Z	−1.8 V to 4 V
Electrostatic discharge	Human Body Model(3)	Y and Z	±9 kV
		All pins	±4 kV
	Charged-Device Model(4)	All pins	±1500 V
	Machine Model(5)	All pins	200 V
Junction temperature, TJ			140°C
Continuous power dissipation, PD			See Dissipation Rating Table

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to the circuit ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114−B.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101−A.
(5) Tested in accordance with JEDEC Standard 22, Test Method A115−A.


Description

The SN65MLVD047 is a quadruple line driver that complies with the TIA/EIA-899 standard, Electrical Characteristics of Multipoint-Low-Voltage Differential Signaling (M−LVDS). The output current of this M−LVDS device has been increased, in comparison to standard LVDS compliant devices, in order to support doubly terminated transmission lines and heavily loaded backplane bus applications. Backplane applications generally require impedance matching termination resistors at both ends of the bus. The effective impedance of a doubly terminated bus can be as low as 30 Ω due to the bus terminations, as well as the capacitive load of bus interface devices. SN65MLVD047 drivers allow for operation with loads as low as 30 Ω. The SN65MLVD047 devices allow for multiple drivers to be present on a single bus. SN65MLVD047 drivers are high impedance when disabled or unpowered. Driver edge rate control is incorporated to support operation. The M−LVDS standard allows up to 32 nodes (drivers and/or receivers) to be connected to the same media in a backplane when multiple bus stubs are expected from the main transmission line to interface devices. The SN65MLVD047 provides 9-kV ESD protection on all bus pins.