SN65MLVD129

Features:

` LVTTL Receiver and Eight Line Drivers Configured as an 8-Port M-LVDS Repeater − SN65MLVD128
` 2 LVTTL Receivers and Eight Line Drivers Configured as Dual 4-Port M-LVDS Repeaters
    − SN65MLVD129
` Drivers Meet or Exceed the M-LVDS Standard (TIA/EIA-899)
` Low-Voltage Differential 30-Ω to 55-Ω Line Drivers for Data Rates(1) Up to 250 Mbps or
   Clock Frequencies Up to 125 MHz
` Power Up/Down Glitch Free
` Controlled Driver Output Voltage Transition Times for Improved Signal Quality
` Bus Pins High Impedance When Disabled or VCC 1.5 V
` Independent Enables for each Driver
` Output-to-Ouput Skew tsk(o) 160 ps Part-to-Part Skew tsk(pp) 800 ps
` Single 3.3-V Voltage Supply
` Bus Pin ESD Protection Exceeds 9 kV
` Packaged in 48-Pin TSSOP (DGG)

Application

· AdvancedTCA^TM (ATCA^TM) Clock Bus Driver
· Clock Distribution
· Data and Clock Repeating Over Backplanes and Cables
· Cellular Base Stations
· Central Office Switches
· Network Switches and Routers


Specifications

			SN65MLVD128, 129
Supply voltage range(2), VCC			−0.5 V to 4 V
Input voltage range, VI		D, EN	−0.5 V to 4 V
Output voltage range, VO		A or B	−1.8 V to 4 V
Electrostatic discharge	Human Body Model(3)	A, B	±9 kV
		All pins	±4 kV
	Charged-Device Model(4)	All pins	±1500 V
	Machine Model(5)	All pins	200 V
Continuous power dissipation			See Dissipation Rating Table

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114−B.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101−A.
(5)Tested in accordance with JEDEC Standard 22, Test Method A115−A.


Description

The SN65MLVD128 and SN65MLVD129 are LVTTL-to-M−LVDS translators/repeaters. Outputs comply with the M−LVDS standard (TIA/EIA-899) and are optimized for data rates up to 250 Mbps, and clock frequencies up to 125 MHz. The driver outputs of SN65MLVD128 and SN65MLVD129 have been designed to support multipoint buses presenting loads as low as 30 Ω and incorporates controlled transition times for backbone operation.

M-LVDS compliant SN65MLVD128 and SN65MLVD129 allow for 32 nodes on a common bus, providing a high-speed replacement for RS-485 devices when lower common-mode voltage range and lower output signaling levels are acceptable. The SN65MLVD128 and SN65MLVD129 provide separate driver enables, allowing for independent control of each output signal.

Intended applications for SN65MLVD128 and SN65MLVD129 include transmission of clock signals from a central clock module, as well as translation and buffering of data or control signals for transmission through a controlled impedance backplane or cable.