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SN74ABT16853

Features: ` Members of the Texas Instruments WidebusTM Family` State-of-the-Art EPIC-II BE BiCMOS Design Significantly Reduces Power Dissipation` Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17` Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C` Distributed VCC an...

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SN74ABT16853: Features: ` Members of the Texas Instruments WidebusTM Family` State-of-the-Art EPIC-II BE BiCMOS Design Significantly Reduces Power Dissipation` Latch-Up Performance Exceeds 500 mA Per JEDEC Standa...

SN74ABT16853 Data Sheet

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Part Number:
SN74ABT16853
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

` Members of the Texas Instruments WidebusTM Family
` State-of-the-Art EPIC-II BE BiCMOS Design Significantly Reduces Power Dissipation
` Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
` Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
` Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
` Flow-Through Architecture Optimizes PCB Layout
` High-Drive Outputs (32-mA IOH, 64-mA IOL)
` Parity-Error Flag With Parity Generator/Checker
` Latch for Storage of the Parity-Error Flag ` Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .  . . . . . . . . .0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . 0.5 V to 5.5 V
Current into any output in the low state, IO:SN54ABT16853  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .96 mA
SN74ABT16853  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 mA
Input clamp current, IIK (VI < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . .  50 mA
Package thermal impedance, JA (see Note 2): DGG package  . . . . . . . . . . . . . . . . . . . . . . .  . . . .81°C/W
                                                                           DL package  . . . . . . . . . . . . . . . . . . . . .  . . . . . . .74°C/W
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .65°C to 150°C


Description

The 'ABT16853 dual 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus, with its corresponding parity bit, the open-collector parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT16853 provide true data at the outputs.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. The parity-error output of 'ABT16853 can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus  to the B bus, and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.

To ensure the high-impedance state of 'ABT16853 during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.




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