SN74ABT32501

These  4ABT32501 36-bit UBTs combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction of 4ABT32501 is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA.

Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. The output of 4ABT32501 enables are complementary (OEAB is active high, and OEBA is active low).

To ensure the high-impedance state of 4ABT32501 during power up or power down, OEBA should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver (B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver (A to B).Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN54ABT32501 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT32501 is characterized for operation from 40°C to 85°C.