SN74ABT3614

Pinout




Specifications

Supply voltage range, V_CC   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.5 V to 7 V
Input voltage range, V_I   (see Note 1) . . . . . . . . . . . . . . . . . . .  0.5 V to V_CC  + 0.5 V
Output voltage range, V_O (see Note 1). . . . . . . . . . . . . . . . . . .  0.5 V to V_CC  + 0.5 V
Input clamp current, I_IK (V_I < 0 or V_I > V_CC )  . . . . . . . . . . . . . . . . . . . . . . . .. . ±20 mA
Output clamp current, I^_OK  (V_O < 0 or V_O > V_CC )  . . . . . . . . . . . . . . . . . . . . . . .±50 mA  
Continuous output current, I_O (V_O  = 0 to V_CC )  . . . . . . . . . . . . . . . . . . . . . . .  ±50 mA 
Continuous current through V_CC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±500 mA
Package thermal impedance, q JA (see Note 2): PCB package . . . . . . . . . . . . . 28°C/W
                                                                            PQ package .  . . . . . . . . . . . . 46°C/W
Storage temperature range, T_stg 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150 °C


Description

The SN74ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read-access times as fast as 10 ns. Two independent 64 × 36 dual-port SRAM FIFOs in this device buffer data in opposite directions. Each SN74ABT3614 FIFO has flags to indicate empty and full conditions and two programmable flags, almost full (AF) and almost empty (AE) to indicate when a selected number of words is stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each SN74ABT3614 mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port.

The SN74ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface.