SN74ABT573ADW

Number of Circuits : 8
Minimum Operating Temperature : - 40 C
Polarity : Non-Inverting
Number of Output Lines : 3
Supply Voltage - Max : 5.5 V
Maximum Operating Temperature : + 85 C
Package / Case : SOIC-20
Low Level Output Current : 32 mA
Packaging : Tube
Supply Voltage - Min : 4.5 V
Logic Type : Transparent D-Type Latch
Logic Family : 74ABT
High Level Output Current : - 32 mA
Propagation Delay Time : 5.7 ns at 5 V


Features:

` Typical V<sub>OLP</sub> (Output Ground Bounce) <1 V at V<sub>CC</sub> = 5 V, T<sub>A</sub> = 25
` High-Drive Outputs (−32-mA I_OH, 64-mA I_OL)
` Ioff Supports Partial-Power-Down Mode Operation
` Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17
` ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)


Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  −0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V_O...−0.5 V to 5.5 V
Current into any output in the low state, I_O: SN54ABT573 . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT573A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 mA
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . .  −18 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, JA (see Note 2): DB package . . . . . . .70/W
(see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58/W
(see Note 2): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78/W
(see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . .  −65 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and  functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.

Description

These SN74ABT573ADW  8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

A buffered output-enable (OE) input of SN74ABT573ADW can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state of SN74ABT573ADW during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This SN74ABT573ADW device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Parameters:

Technical/Catalog Information	SN74ABT573ADW
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Logic Type	D-Type Transparent Latch
Independent Circuits	1
Circuit	8:8
Output Type	Tri-State
Current - Output High, Low	32mA, 64mA
Mounting Type	Surface Mount
Package / Case	20-SOIC (7.5mm Width)
Packaging	Tube
Operating Temperature	-40°C ~ 85°C
Delay Time - Propagation	4ns
Voltage - Supply	4.5 V ~ 5.5 V
Drawing Number	296; 4040000-4; DW; 20
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN74ABT573ADW SN74ABT573ADW 296 1045 5 ND 29610455ND 296-1045-5