SN74ABT821A

Features:

State-of-the-Art EPIC-B^tm BiCMOS Design Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
High-Impedance State During Power Up and Power Down
High-Drive Outputs (32-mA IOH, 64-mA IOL)
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs


Pinout




Specifications

Supply voltage range, VCC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . .  . . . .0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT821  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 96 mA
SN74ABT821A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .  . . .  . . . . . . . . . . . . .  . . . . . . .  .  .  . . . .  . .. 128 mA
Input clamp current, IIK (VI < 0)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . 18 mA
Output clamp current, IOK (VO < 0)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, JA (see Note 2): DB package  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 104°C/W
DW package   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .  . 81°C/W
NT package   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . .  . . . . . . .  . . 67°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 65°C to 150°C


Description

These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the SN74ABT821A devices provide true data at the Q outputs.The SN54ABT821 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT821A is characterized for operation from 40°C to 85°C.