SN74ABTH16823

Features:

 Members of the Texas Instruments Widebus^TE Family
 State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation
 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
 High-Impedance State During Power Up and Power Down
 Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
 Flow-Through Architecture Optimizes PCB Layout
 High-Drive Outputs (32-mA IOH, 64-mA IOL)
 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
 Package Options Include Plastic 300-mil
 Shrink Small-Outline (DL) and Thin Shrink
 Small-Outline (DGG) Packages and 380-mil
 Fine-Pitch Ceramic Flat (WD) Package
 Using 25-mil Center-to-Center Spacings

Pinout




Specifications

Supply voltage range, V_CC . . . . . . . .  . . .. . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I (see Note 1) ... . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V_O . 0.5 V to 5.5 V
Current into any output in the low state, I_O: SN54ABTH16823 .. . . . . . . . . . . . . . . 96 mA
                                                                       SN74ABTH16823 .. . ... . . . . . . . . . . 128 mA
                                                                       Input clamp current, I_IK (V_I < 0)  . . 18 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, qJA (see Note 2): DGG package . . . . . . . . . . . . . . . 81°C/W
                                                                           DL package. . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T_stg . . . .  .  . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C 


Description

These  'ABTH16823 18-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-mpedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.   

The 'ABTH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock.