SN74AC563

 3-State Inverting Outputs Drive Bus Lines Directly
 Full Parallel Access for Loading
 Flow-Through Architecture to Optimize PCB Layout
 EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (N) and Ceramic (J) DIPs

The 'AC563 are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE) input of  'AC563  can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the latches. Old data of  'AC563  can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AC563 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AC563 is characterized for operation from 40°C to 85°C.