SN74AHCT16373

Features:

Members of the Texas Instruments Widebus(TM) Family
EPIC(TM) (Enhanced-Performance Implanted CMOS) Process
Inputs Are TTL-Voltage Compatible
Distributed V_CC  and GND Pins Minimize High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 250 mA Per
ESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings


Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . .  0.5 V to 7 V
Input voltage range, V_I  (see Note 1)  . . . . . . . . . . . . .. .   0.5 V to 7 V
Output voltage range, V_O   (see Note 1)  . . . . .  0.5 V to V_CC   + 0.5 V
Input clamp current, I_IK  (V_I < 0)  . . . . . . . . . . .  . . . . . . . . . .  20 mA
Output clamp current, I_OK   (V_O  < 0 or V_O  > V_CC )  . . . . . . .  ± 20 mA
Continuous output current, I_O  (V_O  = 0 to V_CC )  . . . .  . . . .  ± 25 mA
Continuous current through each V_C C  or GND  . . . . . . .  . .  ± 75 mA
Package thermal impedance, q JA (see Note 2): DGG package  . . . .  . . . . . . . . 70°C/W
                                                                            DGV package  . . . . . . . .. . . . . 58°C/W
                                                                            DL package  . . . . . . . . .  . . . . 63°C/W
Storage temperature range, T_stg  . . . . . . . . . . . . 65° C to 150° C
 


Description

The 'AHCT16373 devices are 16-bit transparent 2Q7 22 27 2D7 D-type latches with 3-state outputs designed 2Q8 2D8 specifically for driving highly capacitive or 23 26 2OE 2LE relatively low-impedance loads.  'AHCT16373  are 24 25 particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, andworking registers.

These  'AHCT16373  devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input of  'AHCT16373  can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state of  'AHCT16373  during power up or power down, OE should be tied to V_CC  through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.The SN54AHCT16373 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AHCT16373 is characterized for operation from 40°C to 85°C.