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SN74AHCT367

Features: Inputs Are TTL-Voltage Compatible True Outputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)PinoutSpecificationsSupply voltage range, VCC. . . . ...

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SN74AHCT367: Features: Inputs Are TTL-Voltage Compatible True Outputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Mod...

SN74AHCT367 Data Sheet

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Part Number:
SN74AHCT367
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Inputs Are TTL-Voltage Compatible
True Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
      2000-V Human-Body Model (A114-A)
      200-V Machine Model (A115-A)
      1000-V Charged-Device Model (C101)


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI(see Note 1) . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . 0.5 V to VCC+ 0.5 V
Input clamp current, IIK(VI< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK(VO< 0 or VO > VCC). . . . . . . . . . . . . . . .±20 mA
Continuous output current, IO(VO= 0 to VCC) . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . ±75 mA
Package thermal impedance, JA (see Note 2):D package . . . . . . .73°C/W
                                                                         DB package. . . . . . .82°C/W
                                                                         DGV package . . . . 120°C/W
                                                                         N package . . . . . . . .67°C/W
                                                                         NS package . . . . . . .64°C/W
                                                                         PW package . . . . . .108°C/W
Storage temperature range, Tstg. . . . . . . . . . . . . . . . . . . . 65°C to 150°C



Description

The 'AHCT367 devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as dual 4 line and 2-line buffers/drivers with active-low output-enable (1OE  and 2OE ) inputs. When OE  is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high impedance state.

To ensure the high-impedance state of 'AHCT367  during power up or power down, OE  should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.




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