SN74AHCT573

Features:

EPIC^tm (Enhanced-Performance Implanted CMOS) Process
Inputs Are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per JESD 17
Package Options Include Plastic
    Small-Outline (DW), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers(FK), and Standard Plastic (N) and Ceramic (J) DIPs


Pinout




Specifications


Supply voltage range, V_CC . . . . .. . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I (see Note 1)   . . . . . . . . . . . . . . . . 0.5 V to 7 V
Output voltage range, VO (see Note 1). . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . .. . . . . . . . . . . . . . . . . 20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC)  . . . . . . . . . . . . . ±20 mA
Continuous output current, I_O (V_O = 0 to V_CC) .  . . . . . . . . . . . . . ±25 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . ±75 mA
Package thermal impedance, JA (see Note 2): DB package. . . . . 70°C/W
                                                                           DGV package  . . . 92°C/W
                                                                           DW package  . . . . 58°C/W
                                                                           N package . . . . . . 69°C/W
                                                                           NS package . . . . . 60°C/W
                                                                           PW package . . . . . 83°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . 65°C to 150°C 


Description

The 'AHCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.When LE is low, the Q outputs are latched at the logic levels of the D inputs.

A buffered output-enable (OE) input of 'AHCT573 can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.