Flip Flops Dual w/Clear Preset
SN74AHCT74RGYR: Flip Flops Dual w/Clear Preset
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| Number of Circuits : | 2 | Logic Family : | 74AH | ||
| Logic Type : | D-Type Flip-Flop | Polarity : | Inverting/Non-Inverting | ||
| Input Type : | Single-Ended | Output Type : | Differential | ||
| Propagation Delay Time : | 8.8 ns | High Level Output Current : | - 8 mA | ||
| Low Level Output Current : | 8 mA | Supply Voltage - Max : | 5.5 V | ||
| Maximum Operating Temperature : | + 85 C | Mounting Style : | SMD/SMT | ||
| Package / Case : | QFN-14 | Packaging : | Reel |

Supply voltage range, VCC ...................................................0.5 V to 7 V
Input voltage range, VI (see Note 1) ................................... 0.5 V to 7 V
Output voltage range, VO (see Note 1) .................. 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) .................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) ........................... ±20 mA
Continuous output current, IO (VO = 0 to VCC)...............................±25 mA
Continuous current through VCC or GND .........................................±50 mA
Package thermal impedance, JA (see Note 2): D package............86°C/W
(see Note 2): DB package .......... 96°C/W
(see Note 2): DGV package ......127°C/W
(see Note 2): N package...............80°C/W
(see Note 2): NS package............. 76°C/W
(see Note 2): PW package .........113°C/W
(see Note 3): RGY package............ 47°C/W
Storage temperature range, Tstg .................................... 65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
The 'AHCT74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,data at the D input of 'AHCT74 can be changed without affecting the levels at the outputs.
| Technical/Catalog Information | SN74AHCT74RGYR |
| Vendor | Texas Instruments (VA) |
| Category | Integrated Circuits (ICs) |
| Mounting Type | Surface Mount |
| Package / Case | 14-VQFN |
| Function | Set and Reset |
| Number of Bits per Element | 1 |
| Number of Elements | 2 - Dual |
| Current - Output High, Low | 8mA, 8mA |
| Output Type | Differential |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Packaging | Cut Tape (CT) |
| Operating Temperature | -40°C ~ 85°C |
| Delay Time - Propagation | 1ns |
| Frequency - Clock | 140MHz |
| Voltage - Supply | 4.5 V ~ 5.5 V |
| Drawing Number | 296; 4203539-2; RGY; 14 |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | SN74AHCT74RGYR SN74AHCT74RGYR 296 13914 1 ND 296139141ND 296-13914-1 |