SN74ALS845

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This SN74ALS845 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The SN74ALS845 eight latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs.

Because the clear (CLR) and preset (PRE) inputs are independent of the clock (CLK) input, taking CLR low causes the eight Q outputs to go low. Taking PRE low causes the eight Q outputs to go high. When both PRE and CLR are taken low, the outputs follow the preset condition. The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a normal logic state (high or low levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. The output enables do not affect the internal operation of the latches. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.The -1 version of the SN74ALS845 is identical to the standard version, except that the recommended maximum IOL for the -1 version is increased to 48 mA.

The SN74ALS845 is characterized for operation from 0°C to 70°C.