PinoutSpecificationsSupply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 7 VInput voltage, VI (OE, RD, EN, CLK, CLR, and T/C) . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 7 VVoltage appl...
SN74ALS996: PinoutSpecificationsSupply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 7 VInput voltage, VI (OE, RD, EN, CLK...
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Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 7 V
Input voltage, VI (OE, RD, EN, CLK, CLR, and T/C) . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 7 V
Voltage applied to D inputs and to disabled 3-state outputs . . . . . . . . . . . . . . . . . .. . . . . . . . . 5.5 V
Operating free-air temperature range, TA: SN54ALS996 . . . . . . . . . . . . . . . . . . 55 to 125
SN74ALS996 . . . . . . . . . . . . . . . . . . .. . . . 0 to 70
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150
These SN54ALS996 and SN74ALS996 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability.
The SN54ALS996 and SN74ALS996 edge-triggered flip-flops enter the data on the low-to-high transition of the clock (CLK) input when the enable (EN) input is low. Data can be read back onto the data inputs by taking the read (RD) input low, in addition to having EN low. When EN is high, both the read-back and write modes are disabled. Transitions onEN should only be made with CLK high to prevent false clocking.
The polarity of the Q outputs can be controlled by the polarity (T/C) input. When T/C is high, Q is the same as is stored in the flip-flops. When T/C is low,the output data is inverted. The Q outputs can be placed in the high-impedance state by taking the output-enable (OE) input high. OE does not affect the internal operation of the register. Old data can be retained or new data can be entered while the outputs are off. A low level at the clear (CLR) input resets the internal registers low. The clear function of SN54ALS996 and SN74ALS996 is asynchronous and overrides all other register functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum IOL for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996. In the SN54ALS996 and SN74ALS996 , the SN54ALS996 is characterized for operation over the full military temperature range of 55 to 125. The SN74ALS996 is characterized for operation from 0 to 70.