SN74ALVC126

 EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
 Latch-Up Performance Exceeds 250 mA Per JESD 17
 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW)
Packages

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . 0.5 V to 4.6 V
Input voltage range, V_I (see Note 1) . . . . . . . . . .. . . . . . .. . . . . . . . 0.5 V to 4.6 V
Output voltage range, V_O (see Notes 1 and 2) . .  . . . . . .. . . 0.5 V to VCC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . .. . . . . .. . . . .  . . . . . 50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . .  . . . . .. ... . .. . . . . . 50 mA
Continuous output current, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . .. . . . . . . . . . . ±100 mA
Package thermal impedance, _JA (see Note 3): D packag. . . . . . . .. .  . . . . 127°C/W
                                                                          DGV package . . . ... . . . . .  182°C/W
                                                                          PW package . . . .. . . . . . . . 170°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . .  . . .. . . . . . . . 65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.The SN74ALVC126 is characterized for operation from 40°C to 85°C.