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SN74ALVC16373

Features: Member of the Texas Instruments WidebusTM FamilyEPICTM(Enhanced-Performance Implanted CMOS) Submicron ProcessTypical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°CTypical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°CBus Hold on Data Inputs Eliminates t...

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SN74ALVC16373: Features: Member of the Texas Instruments WidebusTM FamilyEPICTM(Enhanced-Performance Implanted CMOS) Submicron ProcessTypical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°CTypical...

SN74ALVC16373 Data Sheet

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Part Number:
SN74ALVC16373
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

 Member of the Texas Instruments WidebusTM Family
 EPICTM(Enhanced-Performance Implanted CMOS) Submicron Process
 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
 Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
 ESD Protection Exceeds 2000 V Per MIL-STD-833C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
 Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
 Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, VI: (except I/O ports) (see Note 1) . . . . . . . . . . . .. . . .  . . . . ..0.5 V  to 4.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .±50 mA
Continuous current through VCC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ±100mA
Maximum power package dissipation at TA = 55°C (in still air)(see Note 2):DGG package  . .  0.85 W
                                                                                                                     DL package . .. . . . 1.4 W
Storage temperature range ,Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .65°C to 150°C 


Description

This SN74ALVC16373 16-bit transparent D-type latch is designed for 3.3-V VCC operation; it is tested at 2.5-V, 2.7-V, and 3.3-V VCC.

The SN74ALVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (highor low-logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVC16373 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN74ALVC16373 is characterized for operation from 40°C to 85°C.




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