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SN74ALVC16901

Features: Member of the Texas Instruments WidebusTM FamilyEPICTM (Enhanced-Performance Implanted CMOS) Submicron ProcessUBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked ModeSimultaneously Generates and Checks ParityOp...

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SeekIC No. : 004498240 Detail

SN74ALVC16901: Features: Member of the Texas Instruments WidebusTM FamilyEPICTM (Enhanced-Performance Implanted CMOS) Submicron ProcessUBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flop...

SN74ALVC16901 Data Sheet

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Part Number:
SN74ALVC16901
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

 Member of the Texas Instruments WidebusTM Family
 EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
 UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
 Simultaneously Generates and Checks Parity
 Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions
 Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
 Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
 Packaged in Thin Shrink Small-Outline (DGG) Package


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, VI: (except I/O ports) (see Note 1) . . . . . . . . . . . .. . . .  . . . . ..0.5 V  to 4.6 V
Input voltage range, VI:(I/O ports) (see Notes 1 and 2). . . . . . . . . . . . . . . .   0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . .  . . .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .±50 mA
Continuous current through VCC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ±100mA
Maximum power package dissipation at TA = 55°C (in still air)(see Note 3) . . . . . . . . . . . .  . .  . . 1 W
Storage temperature range ,Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .65°C to 150°C  


Description

This 18-bit (dual-octal) noninverting registered transceiver is designed for 2.7-V to 3.6-V VCC operation.The SN74ALVC16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.

The SN74ALVC16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVC16901 is available in TI's thin shrink small-outline (DGG) package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN74ALVC16901 is characterized for operation from 40°C to 85°C.




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