SN74ALVC7803

The SN74ALVC7803 FIFO is suited for buffering asynchronous data paths at 50-MHz clock rates and 13-ns access times and is designed for 3-V to 3.6-V VCC operation. The 56-pin shrink smalloutline (DL) package offers greatly reduced board space over DIP, PLCC, and conventional SOIC packages. Two devices can be configured for
bidirectional data buffering without additional logic.

The write clock (WRTCLK) and read clock (RDCLK) of SN74ALVC7803 should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.

The SN74ALVC7803 FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.