PinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .0.5 V to 4.6 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 VOutput voltage range, VO (see Notes 1 ...
SN74ALVCH162835: PinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .0.5 V to 4.6 VInput voltage range, VI (see Note 1) . . . . . . . . . ....
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

This SN74ALVCH162835 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The SN74ALVCH162835 device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state.
The output port of SN74ALVCH162835 includes equivalent 26- series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state of SN74ALVCH162835 during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVCH162835 is characterized for operation from 40°C to 85°C.