SN74ALVCH16373

Features:

Member of the Texas Instruments Widebus(TM) Family
EPIC (TM) (Enhanced-Performance Implanted CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JESD 17
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages


Pinout




Specifications

Supply voltage range, V_CC   . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . .. 0.5 V to 4.6 V
Output voltage range, V_O  (see Notes 1 and 2)  . .. 0.5 V to V_CC  + 0.5 V
Input clamp current, I_IK  (V_I < 0)  . . . . . . . . . . . . . . . . . .......... . . . 50 mA
Output clamp current, I_OK  (V_O  < 0)  . . . . . . . . . . . . . . . . . . . . .... 50 mA
Continuous output current, I_O   . . . . . . . . . . . . . . . . . . . . . . . .  . .  ±50 mA
Continuous current through each V_CC  or GND  . . . . . . . . . . . .. .  ±100 mA
Package thermal impedance, JA (see Note 3): DGG package .. . . 89°C/W
                                                                           DL package . .. . .. 94°C/W
Storage temperature range, T_stg  65. . . . . . . . . . . . . . . . . . . .  C to 150 C  


Description

This SN74ALVCH16373 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V V_CC  operation.

The SN74ALVCH16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.