SN74ALVCH16646DGG

This SN74ALVCH16646DGG 16-bit bus transceiver and register isdesigned for 1.65-V to 3.6-V V_CC operation.The SN74ALVCH16646 can be used as two 8-bittransceivers or one 16-bit transceiver. Data on theA or B bus is clocked into the registers on thelow-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74ALVCH16646.

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in eitherregister or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparentmode) data. The SN74ALVCH16646DGG circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexerduring the transition between stored and real-time data. DIR determines which bus receives data when OE islow. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in theother register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. To ensure the high-impedance state of SN74ALVCH16646DGG during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVCH16646 is characterized for operation from 40°C to 85°C.