SN74ALVCH16827

Features: · Member of the Texas Instruments Widebus E Family· EPIC E (Enhanced-Performance Implanted CMOS) Submicron Process· ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)· Latch-Up Performance Exceeds 250 mA Per JESD 17· Bus Hold...

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SN74ALVCH16827 Picture
SeekIC No. : 004498301 Detail

SN74ALVCH16827: Features: · Member of the Texas Instruments Widebus E Family· EPIC E (Enhanced-Performance Implanted CMOS) Submicron Process· ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 ...

floor Price/Ceiling Price

Part Number:
SN74ALVCH16827
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Features:

· Member of the Texas Instruments
  Widebus E Family
· EPIC E (Enhanced-Performance Implanted
  CMOS) Submicron Process
· ESD Protection Exceeds 2000 V Per
  MIL-STD-883, Method 3015; Exceeds 200 V
  Using Machine Model (C = 200 pF, R = 0)
· Latch-Up Performance Exceeds 250 mA Per JESD 17
· Bus Hold on Data Inputs Eliminates the
  Need for External Pullup/Pulldown Resistors
· Package Options Include Plastic 300-mil
  Shrink Small-Outline (DL) and Thin Shrink
  Small-Outline (DGG) Packages



Pinout

  Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±100 mA
Package thermal impedance, qJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.



Description

This 1-bit to 20-bit address register/driver is designed for 1.65-V to 3.6-V VCC operation. This device is ideal for use in applications in which a single address bus is driving four separate memory locations. The SN74ALVCH162832 can be used as a buffer or a register, depending on the logic level of the select (SEL) input.

When SEL is a logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by the two output-enable (OE) inputs. Each OE controls two groups of seven outputs. When SEL is a logic low, the device is in the register mode. The SN74ALVCH162832  register is an edge-triggered D-type flip-flop. On the positive transition of the clock (CLK) input, data at the A inputs is stored in the internal registers. OE controls operate the same as in the buffer mode.

When OE of SN74ALVCH162832  is a logic low, the outputs are in a normal logic state (high or low logic level). When OE is a logic high, the outputs are in the high-impedance state.Neither SEL nor OE affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.The outputs, which are designed to sink up to 12 mA, include equivalent 26-W resistors to reduce overshoot and undershoot.

 


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