SN74ALVCH32501

􀀀 ·Member of the Texas Instruments Widebus™ Family
􀀀 ·EPIC ™ (Enhanced-Performance Implanted CMOS) Submicron Process
􀀀 ·UBT ™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
􀀀 ·Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
􀀀 ·ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
􀀀 ·Latch-Up Performance Exceeds 250 mA Per JESD 17
􀀀 ·Packaged in Plastic Fine-Pitch Ball Grid Array Package

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range, V_I: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . .  . . . . . . . . 0.5 V to 4.6 V
                                       I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . .. . . . . . 0.5 V to V_CC + 0.5 V
Output voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 50 mA
Continuous output current, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ±50 mA
Continuous current through each V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ±100 mA
Package thermal impedance, _JA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 39°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.

This 36-bit universal bus transceiver is designed for 1.65-V to 3.6-V V_CC operation.

This SN74ALVCH32501 device can be used as two 18-bit transceivers or one 36-bit transceiver. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The SN74ALVCH32501 output enables are complementary (OEAB is active high and OEBA is active low).

To ensure the SN74ALVCH32501 high-impedance state during power up or power down, OEBA should be tied to V_CC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH32501 is characterized for operation from 40°C to 85°C.