Features: ` Member of the Texas Instruments Widebus+™ Family
` ESD Protection Exceeds JESD 22
` Bus Hold on Data Inputs Eliminates the Need 2000-V Human-Body Model (A114-A) for External Pullup/Pulldown Resistors
` Latch-Up Performance Exceeds 250 mA Per JESD 17
`ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
Specifications
|
|
|
MIN |
MAX |
UNIT |
|
VCC |
Supply voltage range |
-0.5 |
4.6 |
V |
|
VI |
Input voltage range |
Except I/O and D input ports(2) |
-0.5 |
4.6 |
V |
|
I/O and D input ports(2) (3) |
-0.5 |
VCC + 0.5 |
|
VO |
Output voltage range(2) (3) |
-0.5 |
VCC + 0.5 |
V |
|
IIK |
Input clamp current |
VI < 0 |
|
-50 |
mA |
|
IOK |
Output clamp current |
VO < 0 |
|
-50 |
mA |
|
IO |
Continuous output current |
|
±50 |
mA |
|
|
Continuous current through each VCC or GND |
|
±100 |
mA |
|
JA |
Package thermal impedance(4) |
GKE/ZKE package |
|
40 |
°C/W |
|
Tstg |
Storage temperature range |
-65 |
150 |
°C |
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings re observed.
(3) This value is limited to 4.6 V maximum. (4) The package thermal impedance is calculated in accordance with JESD 51-7.
DescriptionThis SN74ALVCH32973 device contains eight independent noninverting buffers and a 16-bit noninverting bus transceiver and D-type latch designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH32973 is particularly suitable for demultiplexing an address/data bus into a dedicated address bus and dedicated data bus. The device is used where there is asynchronous bidirectional communication between the A and B data bus, and the address signals are latched and buffered on the Q bus. The control-function implementation minimizes external timing requirements.
This SN74ALVCH32973 device can be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit transceiver, and one 16-bit latch. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The transceiver output-enable (TOE) input can be used to disable the transceivers so that the A and B buses effectively are isolated.
When the SN74ALVCH32973 latch-enable (LE) input is high, the Q outputs follow the data (A) inputs When LE is taken low, the Q outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE) input can be used to place the nine Q outputs in either a normal logic state (high or low logic level) or the high-LOE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in the high-impedance state.
To ensure the SN74ALVCH32973 high-impedance state during power up or power down, LOE and TOE should be tied to V CC through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of the drivers.
The eight independent noninverting buffers perform the Boolean function Y = D and are independent of the state of DIR,TOE, LE, and LOE.
The SN74ALVCH32973 A and B I/Os and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
SN74ALVCH32973 Data Sheet
