SN74ALVCHG162280

Features:

`Member of the Texas Instruments Widebus<sup>TM</sup> Family
`EPIC^TM (Enhanced-Performance Implanted CMOS) Sub-Micron Process
`A-Port Outputs Have Equivalent 50- Series Resistors and B-Port Outputs Have Equivalent 20- Series Resistors, So No External Resistors Are Required
`ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
`Latch-Up Performance Exceeds 250 mA Per JESD 17
`Bus-Hold On Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
`Packaged in Thin Very Small-Outline Package


Pinout




Specifications

Supply voltage range, V_CC . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, V_I: Except I/O ports (see Note 1) . . .. . . . . . . . . .  .. . . . .0.5 V to V_CC + 0.5 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .0.5 V to V_CC + 0.5 V
Output voltage range, V_O (see Notes 1 and 2) . . . . . .. . . . . . . . . . . . . . . . .   .0.5 V to VCC + 0.5 V
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Continuous output current, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . .±50 mA
Package thermal impedance, _JA (see Note 3) . . . . .. . . . . . . . . . . . . . . . . . .  . . . .   . . . . . . . 106/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . .65 to 150


Description

The SN74ALVCHG162280 is a 16-bit to 32-bit registered bus exchanger. This SN74ALVCHG162280 device is intended for use in applications where data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. It is designed specifically for low-voltage (3.3-V) VCC operation.
The SN74ALVCHG162280 device provides synchronous data exchange between the two ports, A and B. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input. For data transfer in the B-to-A direction, the select (SEL ) input selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the 1B path, with a single storage register in the 2B path. Data flow is controlled by the active-low output-enable (OE )and direction-control (DIR) inputs. DIR is registered to synchronize the bus direction changes with the clock.