SN74ALVCHR16409

This SN74ALVCHR16409 9-bit, 4-port universal bus exchanger is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCHR16409 allows synchronous data exchange between four different buses. Data flow is controlled by the select (SEL0SEL4) inputs. A data-flow state is stored on the rising edge of the clock (CLK) input if the select-enable (SELEN) input is low. Once a data-flow state has been established, data is stored in the flip-flop on the rising edge of CLK if SELEN is high. The data-flow control logic is designed to allow glitch-free data transmission.

The B outputs, which are designed to sink up to 12 mA, include equivalent 26- series resistors to reduce overshoot and undershoot. When preset (PRE) transitions high, the outputs are disabled immediately, without waiting for a clock pulse. To leave the high-impedance state, both PRE and SELEN must be low and a clock pulse must be applied. To ensure the high-impedance state of SN74ALVCHR16409 during power up or power down, PRE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.