SN74ALVCHR16601

PinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 6.5 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 6.5 V Voltage range applie...

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SeekIC No. : 004498327 Detail

SN74ALVCHR16601: PinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 6.5 VInput voltage range, VI (see Note 1) . . . . . ...

floor Price/Ceiling Price

Part Number:
SN74ALVCHR16601
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/24

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Product Details

Description



Pinout

  Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) 0.5 V to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .±100 mA
Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . .. . . . . . . . . . . . .70°C/W
                                                                         DGV package . . . . . . . . . . . . . . . . . . . . . . . . . .58°C/W
                                                                        DL package . . . . . . . . . . . .. . . . . . .. . . . . . . . . . .63°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.



Description

This SN74ALVCHR16601 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCHR16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but usesOEBA, LEBA, CLKBA, and CLKENBA. The outputs of SN74ALVCHR16601 include equivalent 26-W series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state of SN74ALVCHR16601 during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.




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