SN74AS866A

These Advanced Schottky devices SN74AS866A are capable of performing high-speed arithmetic or logical comparisons on two 8-bit binary or two's complement words. Three fully decoded decisions about words P and Q are externally available at the outputs. These devices are fully expandable to any word length by connecting the totem pole P>Q and P<Q outputs of each stage to the P>Q and P<Q inputs of the next higher-order stage. The cascading paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words. The opencollector P=Q output may be wire-ANDed together.

Both input words P and Q plus all three outputs (P>Q, P<Q, and P = Q) are equipped with latches to provide the designer with temporary data storage for avoiding race conditions. The enable circuitry is implemented with minimal delay times to enhance performance when the devices SN74AS866A are cascaded for longer word lengths. Each latch i transparent when the appropriate latch enable, PLE, QLE, or OLE is high.

The SN74AS866A enable inputs PLE and QLE and data inputs P and Q utilize pnp input transistors to reduce the low-level input current requirement to typically 0.25 mA, which minimizes loading effects.

The Q register may be cleared to zero for a fast comparison of the P word to zero. The SN54AS866 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AS866A is characterized for operation from 0°C to 70°C.