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SN74AUC16373

Features: ` Member of the Texas Instruments Widebus™ Family` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation` Ioff Supports Partial-Power-Down Mode Operation` Sub-1-V Operable` Max tpd of 2 ns at 1.8 V` Low Power Consumption, 20-mA Max ICC` ±8-m...

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SN74AUC16373: Features: ` Member of the Texas Instruments Widebus™ Family` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation` Ioff Supports Partial-Power-Down Mo...

SN74AUC16373 Data Sheet

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Part Number:
SN74AUC16373
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

` Member of the Texas Instruments Widebus™ Family
` Optimized for 1.8-V Operation and Is 3.6-V I/O
  Tolerant to Support Mixed-Mode Signal Operation
` Ioff Supports Partial-Power-Down Mode Operation
` Sub-1-V Operable
` Max tpd of 2 ns at 1.8 V
` Low Power Consumption, 20-mA Max ICC
` ±8-mA Output Drive at 1.8 V
` Latch-Up Performance Exceeds 100 mA Per
  JESD 78, Class II
` ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)


Pinout

Connection Diagram


Specifications

Symbol Parameter MIN MAX Units
VCC Supply voltage range -0.5 3.6 V
VI Input voltage range(2) -0.5 3.6 V
VO Voltage range applied to any output in the high-impedance or power-off state(2) -0.5 3.6 V
VO Output voltage range(2) -0.5 VCC + 0.5 V
IIK Input clamp current VI < 0   -50 mA
IOK Output clamp current VO < 0   -50 mA
IO Continuous output current   ±20 mA
ICC Continuous current through VCC or GND   ±100 mA
IANG Package thermal impedance(3) DCT package   70 °C/W
DCU package   58
YEP/YZP package   42
TSTG Storage temperature range -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.


Description

This SN74AUC16373 16-bit transparent D-type latch is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

low logic levels) or the high-impedance state. In the SN74AUC16373 high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

SN74AUC16373 OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.




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