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SN74AUC1G240

Features: ` Available in the Texas Instruments NanoFree™ Package` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation` Ioff Supports Partial-Power-Down Mode Operation` Sub-1-V Operable` Max tpd of 2.5 ns at 1.8 V` Low Power Consumption, 10-mA Max IC...

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SeekIC No. : 004498480 Detail

SN74AUC1G240: Features: ` Available in the Texas Instruments NanoFree™ Package` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation` Ioff Supports Partial-Power-Do...

SN74AUC1G240 Data Sheet

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Part Number:
SN74AUC1G240
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` Available in the Texas Instruments NanoFree™ Package
` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
` Ioff Supports Partial-Power-Down Mode Operation
` Sub-1-V Operable
` Max tpd of 2.5 ns at 1.8 V
` Low Power Consumption, 10-mA Max ICC
` ±8-mA Output Drive at 1.8 V
` Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
` ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)


Pinout

Connection Diagram


Specifications

 
MIN
MAX
UNIT
VCC Supply voltage range
0.5
3.6
V
VI Input voltage range(2)
0.5
3.6
V
VO Voltage range applied to any output in the high-impedance or power-off state(2)
0.5
3.6
V
VO Output voltage range(2)
0.5
VCC+0.5
V
IIK Input clamp current VI < 0
-50
mA
IOK Output clamp current VO < 0
-50
mA
IO Continuous output current
±20
mA
Continuous current through VCC or GND
±100
mA
JA Package thermal impedance(3) DBV package
206
/W
DCK package
252
YZP package
132
Tstg Storage temperature range
-65
150

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.2 Submit




Description

This SN74AUC1G240 bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC1G240 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

To ensure the SN74AUC1G240 high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This SN74AUC1G240 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.




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