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SN74AUC1G74

Features: ` Available in the Texas Instruments ` Low Power Consumption, 10-mA Max ICC NanoStar™ and NanoFree™ Packages ` ±8-mA Output Drive at 1.8 V` Optimized for 1.8-V Operation and Is 3.6-V I/O ` Latch-Up Performance Exceeds 100 mA Per Tolerant to Support Mixed-Mode Signal JESD 78, ...

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SeekIC No. : 004498483 Detail

SN74AUC1G74: Features: ` Available in the Texas Instruments ` Low Power Consumption, 10-mA Max ICC NanoStar™ and NanoFree™ Packages ` ±8-mA Output Drive at 1.8 V` Optimized for 1.8-V Operation and Is...

SN74AUC1G74 Data Sheet

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Part Number:
SN74AUC1G74
Supply Ability:
5000

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Product Details

Description



Features:

` Available in the Texas Instruments
` Low Power Consumption, 10-mA Max ICC
  NanoStar™ and NanoFree™ Packages
` ±8-mA Output Drive at 1.8 V
` Optimized for 1.8-V Operation and Is 3.6-V I/O
` Latch-Up Performance Exceeds 100 mA Per
  Tolerant to Support Mixed-Mode Signal JESD 78, Class II
  Operation ` ESD Protection Exceeds JESD 22
` Ioff Supports Partial-Power-Down Mode
2000-V Human-Body Model (A114-A) Operation
200-V Machine Model (A115-A)
` Sub-1-V Operable
1000-V Charged-Device Model (C101)


Pinout

Connection Diagram


Specifications

Symbol Parameter MIN MAX Units
VCC Supply voltage range -0.5 3.6 V
VI Input voltage range(2) -0.5 3.6 V
VO Voltage range applied to any output in the high-impedance or power-off state(2) -0.5 3.6 V
VO Output voltage range(2) -0.5 VCC + 0.5 V
IIK Input clamp current VI < 0   -50 mA
IOK Output clamp current VO < 0   -50 mA
IO Continuous output current   ±20 mA
ICC Continuous current through VCC or GND   ±100 mA
IANG Package thermal impedance(3) DCT package   220 °C/W
DCU package   227
YEP/YZP package   102
TSTG Storage temperature range -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.


Description

This SN74AUC1G74 single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. SN74AUC1G74 Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR input overrides the PRE input when they are both low.

SN74AUC1G74 NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.




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