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SN74AUC2G125

Features: • Available in the Texas Instruments NanoStar ™ and NanoFree ™ Packages• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation• I off Supports Partial-Power-Down Mode Operation• Sub-1-V Operable• Max t pd ...

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SeekIC No. : 004498494 Detail

SN74AUC2G125: Features: • Available in the Texas Instruments NanoStar ™ and NanoFree ™ Packages• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operat...

SN74AUC2G125 Data Sheet

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Part Number:
SN74AUC2G125
Supply Ability:
5000

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Product Details

Description



Features:

• Available in the Texas Instruments NanoStar ™ and NanoFree ™ Packages
• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• I off Supports Partial-Power-Down Mode Operation
• Sub-1-V Operable
• Max t pd of 1.8 ns at 1.8 V
• Low Power Consumption, 10 µ A at 1.8 V
• ± 8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)


Pinout

Connection Diagram


Specifications

Symbol Parameter MIN MAX Units
VCC Supply voltage range -0.5 3.6 V
VI Input voltage range(2) -0.5 3.6 V
VO Voltage range applied to any output in the high-impedance or power-off state(2) -0.5 3.6 V
VO Output voltage range(2) -0.5 VCC + 0.5 V
IIK Input clamp current VI < 0   -50 mA
IOK Output clamp current VO < 0   -50 mA
IO Continuous output current   ±20 mA
ICC Continuous current through VCC or GND   ±100 mA
IANG Package thermal impedance(3) DCT package   220 °C/W
DCU package   227
YEP/YZP package   102
TSTG Storage temperature range -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.


Description

This SN74AUC2G125 dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.

 SN74AUC2G125NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

To ensure the SN74AUC2G125 high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This SN74AUC2G125 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For more SN74AUC2G125 information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.




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