SN74AVC126

Pinout




Specifications

Supply voltage range, V_CC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .0.5 V to 4.6 V
Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, V_O
    (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, V_O
    (see Notes 1 and 2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .  .0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .. . . . . .50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .. . . . .50 mA
Continuous output current, I_O  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .. .  . . . . .±50 mA
Continuous current through each V_CC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . .  . . .±100 mA
Package thermal impedance, _JA (see Note 3): D package  . . . . . . . . . . . . . . . . . .  . . . . . .. . .. . .86°C/W
                                                                          DGV package  . . . . . . . . . . . . . . . . . . . . .. . . .  . 127°C/W
                                                                          PW package  . . . . . . . . . . . . . . . . . . . . . . . . . .. .113°C/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .65°C to 150°C 


Description

A SN74AVC126 Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V_OL vs I_OL and V_OH vs I_OH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to TI application reports AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC^TM) Circuitry Technology and Applications, literature number SCEA009.

This SN74AVC126 quadruple bus buffer gate is operational at 1.2-V to 3.6-V V_CC, but is designed specifically for 1.65-V to 3.6-V V_CC operation.

The SN74AVC126 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the SN74AVC126 high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This SN74AVC126 device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC126 is characterized for operation from 40°C to 85°C.