SN74BCT29834

Pinout




Specifications

Supply voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Input voltage, V_I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled I/O port . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . 0°C to 70°C
Storage temperature range . . .. . . . . . . . 65°C to 150°C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.


Description

The SN74BCT29834 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or no an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated.


A 9-bit parity generator/checker of the SN74BCT29834 generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error flag (ERR). ERR is clocked into the register on the rising edge of the CLK input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29834 provides inverting logic.


The SN74BCT29834 is characterized for operation from 0°C to 70°C