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SN74BCT29853

Features: • BiCMOS Process With TTL Inputs and Outputs• State-of-the-Art BiCMOS Design Significantly Reduces Standby Current• Flow-Through Pinout (All Inputs on Opposite Side From Outputs)• Functionally Equivalent to AMD Am29853• High-Speed Bus Transceiver With Parity...

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SeekIC No. : 004498611 Detail

SN74BCT29853: Features: • BiCMOS Process With TTL Inputs and Outputs• State-of-the-Art BiCMOS Design Significantly Reduces Standby Current• Flow-Through Pinout (All Inputs on Opposite Side From ...

SN74BCT29853 Data Sheet

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Part Number:
SN74BCT29853
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• BiCMOS Process With TTL Inputs and Outputs
• State-of-the-Art BiCMOS Design Significantly Reduces Standby Current
• Flow-Through Pinout (All Inputs on Opposite Side From Outputs)
• Functionally Equivalent to AMD Am29853
• High-Speed Bus Transceiver With Parity Generator/Checker
• Parity-Error Flag With Open-Collector Output
• Latch for Storage of the Parity-Error Flag
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)


Pinout

Connection Diagram


Specifications

Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .7 V
Input voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled I/O port  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . 0°C to 70°C
Storage temperature range  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C


Description

The SN74BCT29853 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-erro (ERR)r flag. ERR can be either passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29853 provides true logic.

The SN74BCT29853 is characterized for operation from 0°C to 70°C.




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