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SN74BCT533

Features: • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ• Full Parallel Access for Loading• 3-State Inverting Outputs Drive Bus Lines or Buffer Memory Address Registers• ESD Protection Exceeds 2000 V Per MIL-Std-883C, Method 3015• Package Options Include ...

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SeekIC No. : 004498619 Detail

SN74BCT533: Features: • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ• Full Parallel Access for Loading• 3-State Inverting Outputs Drive Bus Lines or Buffer Memory Address Register...

SN74BCT533 Data Sheet

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Part Number:
SN74BCT533
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
• Full Parallel Access for Loading
• 3-State Inverting Outputs Drive Bus Lines or Buffer Memory Address Registers
• ESD Protection Exceeds 2000 V Per MIL-Std-883C, Method 3015
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (N)


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . .  . .   0.5 V to 7V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to VCC
Input clamp current. .    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .30 mA
Current into any output in the low state . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . 128 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .  .  0°C to70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . .. .65°C to 150°C  


Description

The SN74BCT533 is an 8-bit transparent D-type latch with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse of the levels set up at the D inputs. The SN74BCT533 provides inverted data at its outputs.

A buffered output-enable (OE) input of the SN74BCT533 can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable (OE) input of the SN74BCT533 does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74BCT533 is characterized for operation from 0°C to 70°C.




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