SN74CB3Q6800

Pinout




Specifications

Supply voltage range, VCC   . . . . . . . . . . . . . . . . . . .  . . . . . . . . . −0.5 V to 4.6 V
BIAS supply voltage range, BIASV . . . . . . . . . . . .. . . . . . . . . .. . . . .−0.5 V to 7 V
Control input voltage range, VIN (see Notes 1 and 2)    . . . . . . .. . −0.5 V to 7 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . ..−0.5 V to 7 V
Control input clamp current, IIK (VIN < 0) . . . . . . .  . . . . . .. . . . .  . . . . . . −50mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . .  . . .  . . . . . .. .  . . ... .−50 mA
ON-state switch current, II/O (see Note 4). . . . . . . . . . . . .  . . . . . . .. . . ±64 mA
Continuous current through VCC or GND terminals  . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, JA (see Note 5): DBQ package. . . . . . . . .61°C/W
                                                                           DGV package. . . . . .  . . 86°C/W
                                                                           PW package. . . . .  . . . .88°C/W
Storage temperature range, Tstg . . . . . . . . . . .. . . . . .  . . . . . .−65°C to 150°C 


Description

The SN74CB3Q6800 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q6800 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q6800 is a 10-bit bus switch with a single output-enable (ON) input. When ON is low, the 10-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When ON is high, the 10-bit bus switch is OFF and a high-impedance state exists between the A and B ports. The B port is precharged to bias voltage (BIASV) through the equivalent of a 10-kΩ resistor when ON is high, or if the device is powered down (VCC = 0 V).

During insertion (or removal) of a card into (or from) an active bus, the card's output voltage may be close to GND. When the connector pins make contact, the card's parasitic capacitance tries to force the bus signal to GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch with precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers on the active bus. This method will ensure that any glitch produced by insertion (or removal) of the card will not cross the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise.

This SN74CB3Q6800 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the SN74CB3Q6800 high-impedance state during power up or power down, ON should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.