SN74CBTLV3857

Features:

􀀀 Enable Signal Is SSTL_2 Compatible
􀀀 Flow-Through Architecture Optimizes PCB Layout
􀀀 Designed for Use With 200 Mbit/s Double Data-Rate (DDR) SDRAM Applications
􀀀 Switch On-State Resistance Is Designed to Eliminate Series Resistor to DDR SDRAM
􀀀 Internal 10-kW Pulldown Resistors to Ground on B Port
􀀀 Internal 50-kW Pullup Resistor on Output-Enable Input
􀀀 Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
􀀀 Package Options Include Shrink Small-Outline (DBQ), Thin Very Small-Outline (DGV), Small-Outline (DW), and Thin Shrink Small-Outline (PW) Packages


Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range (OE only), V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input voltage range (except OE), V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 48 mA
Input clamp current, I_IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 50 mA
Package thermal impedance, _JA (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W
                                                                          DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W
                                                                          DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
                                                                          PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

             2. The package thermal impedance is calculated in accordance with JESD 51.


Description

This 10-bit FET bus switch is designed for 3-V to 3.6-V V_CC operation and SSTL_2 output-enable (OE) input levels.

When OE of the SN74CBTLV3857 is low, the 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. There are 10-kW pulldown resistors to ground on the B port.

The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data path.

The SN74CBTLV3857 is characterized for operation from 40°C to 85°C.