SN74FB1653

    The SN74FB1653 device contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. It is specifically designed to be compatible with IEEE Std 1194.1-1991 (BTL).

    The SN74FB1653 A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B  port when the A-port output enable (OEA) is high. When OEA is low or when V_CC(5 V) is typically less than 2.5 V, the A outputs are in the high-impedance state.

    
    The SN74FB1653 B port operates at BTL signal levels. The open-collector B ports are specified to sink 100 mA. Two output enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or V_CC(5 V) is typically less than 2.5 V, the B port is turned off.

    The SN74FB1653 clock-select inputs (2SEL1 and 2SEL2) are used to configure the TTL-to-BTL clock paths and delays. Refer to the Mux-Mode Delay table.

    SN74FB1653 BIAS V_CC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected. BG V_CC and BG GND are the supply inputs for the bias generator.

    SN74FB1653 V_REF is used to bypass the internal threshold reference voltage of the device. It is recommended that this pin be decoupled with a 0.1-µF capacitor.

    SN74FB1653 Enhanced heat-dissipation techniques should be used when operating this device from: (a) AI to A0 at frequencies greater than 50 MHz, or (b) AI to B , or B to A0 at frequencies greater than 100 MHz.

    The SN74FB1653 is characterized for operation from 0°C to 70°C.