SN74GTL1655

Features:

    Members of the Texas Instruments Widebus^TM Family
    UBT^TM(Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent,Latched, or Clocked Mode
    Translate Between GTL/GTL+ Signal Level and LVTTL Logic Levels
    High-Drive (100 mA),Low-Output-Impedance (12 ) Bus Transceiver (B Port) 
    Edge-Rate-Control Input Configures the B-Port Output Rise and Fall Times
    I_off , Power-Up 3-State, and BIAS V_CC Support Live Insertion
    Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port
    Distributed V_CC and GND-Pin Configuration Minimizes High-Speed Switching Noise
    Package Options Include Thin Shrink Small-Outline (DGG) and Ceramic Quad Flat (HV) Packages

Pinout




Specifications

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V_CC , BIAS V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . .. . 0.5 V to 4.6 V
Input voltage range, V_I(see Note 1): A-port and control pins  . . . . . . . . . .   . .  . . 0.5 V to 4.6 V
                                                           B port, V_ERC , and V_REF    . . . . . . . . . .. . . . . 0.5 V to 4.6 V
 Voltage range applied to any output in the high or power-off state, V_O
(see Note 1): A port  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .. . .  . . 0.5 V to 4.6 V
                      B port  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .. . . . . . . . .  . 0.5 V to 4.6 V
Current into any output in the low state, I_O: A port  . . . . . . . . . . . . . . .  . . . . . .   . . . . . .. .  48 mA
                                                                       B port  . . . . . . . . . . . . . . . . . . .. .  . . . . .. .    200 mA
Current into any A-port output in the high state, I_O (see Note 2)  . . . . . . . . . . . . .  .. . .  . .  48 mA
Continuous current through each V_CC  or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . .. .   . ... . 100 mA
Input clamp current, I_IK(V_I < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .  50 mA
Output clamp current, I^_OK  (V^_O< 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..  . .  . . . 50 mA
Package thermal impedance, q JA (see Note 3)  . . . . . . . . . . . . . . . . . . . . . . .  . . . .  . . . . . 55°C/W
Storage temperature range, T_stg 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   . .. .  C to 150 C 


Description

The ^,SN74GTL1655 devices are high-drive (100 mA),low-output-impedance (12 W ) 16-bit universal bus transceivers (UBT) that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They are partitioned as two 8-bit transceivers and combine D-type flip-flops and D-type latches to allow for transparent, latched,and clocked modes of data transfer similar to the'16501 function. These devices of the SN74GTL1655 provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels and output edge control (OEC(TM)). The high drive is suitable for driving double-terminated low-impedance backplanes using incident-wave switching.