SN74GTL16612

The SN74GTL16612 devices are 18-bit UBT^TM  transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC(TM) circuitry.

The user of the SN74GTL16612 has the flexibility of using these devices at either GTL (V_TT = 1.2 V and V_REF = 0.8 V) or the preferredhigher noise margin GTL+ (V_TT= 1.5 V and V_REF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. V is the reference input voltage for the B port.

V_CC (5 V) supplies the internal and GTL circuitry while V_CC (3.3 V) supplies the LVTTL output buffers.