SN74GTLP2034

Supply voltage range, V_CC and BIAS V_CC . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range, V_I (see Note 1): AI port, ERC, and control inputs . .0.5 V to 7 V
B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, V_O
(see Note 1): AO port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . 0.5 V to 4.6 V
Current into any output in the low state, I_O: AO port . . . . . . .  . . . . . . . . . . . 48 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Current into any A-port output in the high state, I_O (see Note 2) . . . . . . . . . 48 mA
Continuous current through each V_CC or GND . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . .  . . .. . . 50 mA
Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . 70/W
                                                                          DGV package . . . . . . .. . . . . . 58/W
                                                                          GQL package . . . . . . . . . . . . . 42/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 65 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V_O > V_CC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

The SN74GTLP2034 is a high-drive, 8-bit, three-wire registered transceiver that provides true LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The SN74GTLP2034 device allows for transparent, latched, and flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and diagnostics monitoring, the same functionality as the SN74FB2033, but with true logic. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 .GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.

The ac specification of the SN74GTLP2034 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either G_TL (V_TT = 1.2 V and V_REF = 0.8 V) or GTLP (V_TT = 1.5 V and V_REF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL Applications, literature number SCEA017.

Normally, the SN74GTLP2034 B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and can be directly driven by TTL or 5-V CMOS devices. VREF is the B-port differential input reference voltage.

This SN74GTLP2034 device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS V_CC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS V_CC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

This SN74GTLP2034 GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between low and high adjusts the B-port output rise and fall times. SN74GTLP2034 allows the designer to optimize system data-transfer rate and signal integrity to the backplane load.

When V_CC SN74GTLP2034 is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OEAB should be tied to V_CC through a pullup resistor and OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.