Features: ` Member of the Texas Instruments Widebus+™ Family
` UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, and Clock-Enabled Modes
` TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
` OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
` Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
` GTLP Buffered CLKAB Signal (CLKOUT)
` LVTTL Interfaces Are 5-V Tolerant
` Medium-Drive GTLP Outputs (50 mA)
` LVTTL Outputs (24 mA/24 mA)
` GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
` Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
` Bus Hold on A-Port Data Inputs
` Distributed VCC and GND Pins Minimize High-Speed Switching Noise
` Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
` ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
Specifications
| |
MIN |
MAX |
UNIT |
VCC
BIAS VCC |
Supply voltage range |
|
-0.5 |
4.6 |
V |
| VI |
Input voltage range(2) |
A-port and control inputs |
0.5 |
7 |
V |
| B port and VREF |
0.5 |
4.6 |
| VO |
Voltage range applied to any output in the high-impedance or power-off state(2) |
A port |
0.5 |
7 |
V |
| B port |
0.5 |
4.6 |
| IO |
Current into any output in the low state |
A port |
|
48 |
mA |
| B port |
|
100 |
| IO |
Current into any A-port output in the high state(3) |
|
48 |
mA |
|
Continuous current through each VCC or GND |
|
±100 |
mA |
| IIK |
Input clamp current |
VI < 0 |
|
-50 |
mA |
| IOK |
Output clamp current |
VO < 0 |
|
-50 |
mA |
| JA |
Package thermal impedance(4) |
|
36 |
°C/W |
| Tstg |
Storage temperature range |
-65 |
150 |
°C |
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
DescriptionThe SN74GTLPH32916 is a medium-drive, 34-bit UBT transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes of data transfer. Additionally, it provides for a copy of CLKAB at GTLP signal levels (CLKOUT) and conversion of a GTLP clock to LVTTL logic levels (CLKIN). The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V),reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 .
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.The ac specification of the SN74GTLPH32916 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels.
Normally, the SN74GTLPH32916 B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage.
This SN74GTLPH32916 device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.
SN74GTLPH32916 Data Sheet
