SN74HC138N

Number of Bits :
Propagation Delay Time :
Supply Voltage - Max : 6 V
Supply Voltage - Min : 2 V
Maximum Operating Temperature : + 85 C
Product : Decoder / Demultiplexer
Number of Lines (Input / Output) : 3 / 8
Packaging : Tube
Logic Family : HC
Mounting Style : Through Hole
Package / Case : PDIP-16


Features:

` Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
` Wide Operating Voltage Range of 2 V to 6 V
` Outputs Can Drive Up To 10 LSTTL Loads
` Low Power Consumption, 80-A Max ICC
` Typical tpd = 15 ns
` ±4-mA Output Drive at 5 V
` Low Input Current of 1 A Max
` Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception


Pinout




Specifications

Supply voltage range, V_CC −0.5 V to 7 V
Input clamp current, I_IK (V_I < 0 or V_I > V_CC) (see Note 1) . . . . . .±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) (see Note 1) . . . ±20 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . . .±25 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . .  ±50 mA
Package thermal impedance, _JA (see Note 2): D package . . . . . . 73/W
DB package . . . . 82/W
N package . . . . . 67/W
NS package . . . . 64/W
PW package . . .108/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . −65 to 150

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

Description

The SN74HC138N devices are designed to be used in high-performance memory-decoding or datarouting applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high of the SN74HC138N enable inputs reduce the need for external gates or inverters when expanding.A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

Parameters:

Technical/Catalog Information	SN74HC138N
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Circuit	1 x 3:8
Independent Circuits	1
Mounting Type	Through Hole
Current - Output High, Low	5.2mA, 5.2mA
Package / Case	16-DIP (300 mil)
Packaging	Tube
Type	Decoder/Demultiplexer
Voltage Supply Source	Single Supply
Operating Temperature	-40°C ~ 85°C
Voltage - Supply	2 V ~ 6 V
Drawing Number	296; 4040049; N; 14, 16, 18, 20
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN74HC138N SN74HC138N 296 1575 5 ND 29615755ND 296-1575-5