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SN74HC164

PinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . 0.5 V to 7 VInput clamp current, IIK(VI < 0 or VI > VCC ) (see Note 1) . . .... . . . . . . ±20 mAOutput clamp current, IOK(VO< 0 or VO> VCC) (see Note 1) . . . . . . . . .. ±...

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SeekIC No. : 004498909 Detail

SN74HC164: PinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . 0.5 V to 7 VInput clamp current, IIK(VI < 0 or VI > VCC ) (see Note 1) . . .... ....

SN74HC164 Data Sheet

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Part Number:
SN74HC164
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Pinout

Connection Diagram


Specifications

Supply voltage range, VCC   . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . .  0.5 V to 7 V
Input clamp current, IIK (VI  < 0 or VI > VCC ) (see Note 1)  . . .  ... . . . . . .   ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1)  . . . . . . . . .  .  ±20 mA
Continuous output current, IO  (VO = 0 to VCC )  . . . . . . . . .. . . . . . . . . . . .  ±25 mA
Continuous current through VCC or GND  . . . . . . . . . . . . . . . . .  . . . . . . . . .  ±50 mA
Package thermal impedance, JA (see Note 2): D package  . . . . . . . . . . . . . . 86/W
                                                                          N package  . . . . . . . . . . . . . . 80/W
                                                                          NS package  . . . . .. . . . . . . . . 76/W
                                                                          PW package  . . . . . . . . . . ..  113/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . .  . . . . . . . . .. . .65 to 150


Description

  These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input of the SN74HC164. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.




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