ApplicationAudioAutomotiveBroadbandDigital ControlMilitaryOptical NetworkingSecurityTelephonyVideo & ImagingWirelessPinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 VInput clamp current, IIK (VI...
SN74HC74: ApplicationAudioAutomotiveBroadbandDigital ControlMilitaryOptical NetworkingSecurityTelephonyVideo & ImagingWirelessPinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . ...
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Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . .±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . .86/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . ...9 6/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . 80/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . 76/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . 113/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65/ to 150
The 'HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE ) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When (PRE ) and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. SN74HC74 Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.