Flip Flops Dual Pos-Edge-Trig J-K Flip-Flop
SN74LS109AN: Flip Flops Dual Pos-Edge-Trig J-K Flip-Flop
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| Number of Circuits : | 2 | Logic Family : | 74LS | ||
| Logic Type : | J-K Flip-Flop | Polarity : | Inverting/Non-Inverting | ||
| Input Type : | Single-Ended | Output Type : | Differential | ||
| Propagation Delay Time : | 40 ns | High Level Output Current : | - 0.4 mA | ||
| Low Level Output Current : | 8 mA | Supply Voltage - Max : | 5.25 V | ||
| Maximum Operating Temperature : | + 70 C | Mounting Style : | Through Hole | ||
| Package / Case : | PDIP-16 | Packaging : | Tube |

| Symbol | Parameter | Min | Typ | Max | Unit |
| VCC | Supply Voltage | 4.75 |
5.0 |
5.25 |
V |
| TA | Operating Ambient Temperature Range | 0 |
25 |
70 |
°C |
| IOH | Output Current - High | -0.4 | mA | ||
| IOL | Output Current - Low | 8.0 |
mA |
The SN74LS109AN consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JKdesign allows operation as a D flip-flop by simply connecting the J and K pins together.